Advanced Reliability, Availability and Safety Design Tools for Industrial Applications

About Dr. Mugnaini's Webinar

Scientific and industrial worlds have started recently to look again with interest to the basic rules to perform reliability, availability and safety analysis and design on complex electro-mechanical systems. The main failure modes on electronic devices and sensors as well as the main techniques for failure mode investigation are of interest in modern system design. Statistical characterization of the main probability density functions and degradation models of innovation is mandatory to build lasting and safe products. The main reliability design techniques such as: fault tree analysis, cut set method, minimal path approach, critical block analysis for reliability are requested by companies worldwide as well as the knowledge of the main failure modes and reliability databases and handbooks as MIL-HDBK217, OREDA, BELLCORE, etc… Maintenance policies with special attention to corrective and preventive ones are also affected by reliability design in terms of advantages and disadvantages when applied to electro-mechanical systems. The main safety standards as IEC61508, IEC 61511 and EN50129, EN50128, EN50126 are usually considered in industrial design. The aim of this talk is to enable companies to develop inner confidence on advanced modelling techniques involving reliability, availability and safe design. Under this spotlight in addition to traditional and well known statistical models, innovative modelling techniques based on statistical data representation will be introduced and tailored to some specific case studies in the fields of bio instruments, transportations and oil & gas contexts.

Accurate Linearity Testing for High Performance Data Converters Using Significantly Reduced Measurement Time and Relaxed Instrumentation

About Dr. Chen's Webinar

Semiconductor chip manufacturing cost consists of die cost, package cost, and test cost. The trends of increasing design complexity, increasing quality needs, and new process nodes and defect models are pushing test cost to the forefront. This is especially true for high-resolution data converters, whose accurate testing requires expensive instruments and is extremely time-consuming. As a result, linearity test of data converters often dominates the overall test cost of SoCs. This talk will present several recently developed techniques for reducing linearity test cost by dramatically reducing measurement time and dramatically relaxing instrumentation requirements.

The IEEE standard for ADC linearity test requires the stimulus signal to be at least 10 times more accurate than the ADC under test. To relax this stringent requirement, the SEIR (stimulus error identification and removal) algorithm is developed to accurately test high-resolution ADCs using nonlinear stimuli. It has been demonstrated by industries that more than 16 bits of ADC test accuracy were achieved using 7-bit linear ramps instead of 20-bit linear ramps as required by IEEE, a relaxation of well over 1000 times on the instrumentation accuracy requirement.

The biggest contributor to test cost is the long measurement time. The recently developed uSMILE (ultrafast Segmented Model Identification for Linearity Errors) algorithm can dramatically reduce the measurement time needed for ADC linearity test. With a system identification approach using a segmented model for the integral nonlinearity, the algorithm can reduce the test time by a factor of over 100 and still achieve test accuracies superior to the standard histogram test method. This method has been extensively validated by industry and has been adopted for production test for multiple product families.

By combining the salient features of both SEIR and uSMILE, the ultrafast stimulus error removal and segmented model identification of linearity errors (USER- SMILE) algorithm is developed. The USER-SMILE algorithm uses two nonlinear signals as input to the ADC under test. One signal is shifted by a constant voltage with respect to the other nonlinear signal. By subtracting the two sets of output codes, input signal is canceled and the nonlinearity of ADC, modeled by a segmented non-parametric INL model, will be identified with the least square method.

A completely on-chip ADC BIST circuit is developed based on the USER-SMILE algorithm and demonstrated on a 28nm CMOS automotive microcontroller. The ADC test subsystem includes a nonlinear DAC as signal generator, a built-in voltage shift generator, a BIST computation engine, and dedicated memory cells. The silicon measurement results show accurate test results. The INL test results are further used to correct ADC linearity errors, thus providing a method for reliably calibrating the ADC. Measurement results demonstrated that the BIST-based calibration method achieved >10dB THD/SFDR improvements over the existing calibration method used by industry.